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asahi kasei [ak4358] ms0203-e-00 2003/02 - 1 - general description the ak4358 is eight channels 24bit dac corresponding to digital audio system. using akm's advanced multi bit architecture for its modulator the ak4358 del ivers a wide dynamic range while preserving linearity for improved thd+n performance. the ak4358 has full differential scf outputs, removing the need for ac coupling capacitors and increasing performance for systems with excessive clock jitter. the ak4358 accepts 192khz pcm data and 1-bit dsd data, ideal for a wide range of applications including dvd-audio and sacd. features ? sampling rate ranging from 8khz to 192khz ? 24bit 8 times digital filter with slow roll-off option ? thd+n: -94db ? dr, s/n: 112db ? high tolerance to clock jitter ? low distortion differential output ? dsd data input available ? digital de-emphasis for 32, 44.1 & 48khz sampling ? zero detect function ? channel independent digital attenuator with soft-transition (3 speed mode) ? soft mute ? 3-wire serial and i 2 c bus p i/f for mode setting ? i/f format: msb justified, lsb justified (16bit, 20bit, 24bit), i 2 s, tdm or dsd ? master clock: 256fs, 384fs, 512f s or 768fs (pcm normal speed mode) 128fs, 192fs, 256fs or 384fs (pcm double speed mode) 128fs or 192fs (pcm quad speed mode) 512fs or 768fs (dsd mode) ? power supply: 4.75 to 5.25v ? 48pin lqfp package scf dac datt dzf lout1+ lout1- scf dac datt rout1+ rout1- scf dac datt lout2+ lout2- scf dac datt rout2+ rout2- scf dac datt lout3+ lout3- scf dac datt rout3+ rout3- audio i/f control register ak4358 mclk lrc k bic k dcl k dsdl1 dsdr1 3-wire or i2c sdti1 sdti2 sdti3 dsdl2 dsdr2 dsdl3 dsdr3 pcm dsd scf dac datt lout4+ lout4- scf dac datt rout4+ rout4- dsdl4 dsdr4 sdti4 192khz 24-bit 8ch dac with dsd input ak4358
asahi kasei [ak4358] ms0203-e-00 2003/02 - 2 - ? ordering guide ak4358vq -40 +85 c 48lqfp AKD4358 evaluation board for ak4358 ? pin layout lout1- rout1+ 1 lout1+ 48 2 dzf3 3 dzf2 4 dzf1 5 cad0 6 acksn 7 pdn 8 bic k 9 mcl k 10 dvdd rout1- 47 lout2+ 46 4 5 44 rout2- 43 lout3+ 42 lout3- 41 rout3+ 40 rout3- 39 lout4+ 38 sdti4 13 sdti1 14 sdti2 15 sdti3 16 lrck 17 18 cclk/scl 19 cdti/sda 20 csn/cad1 21 dclk 22 dsdl4 23 36 35 34 33 32 31 30 29 28 27 26 a vss a vdd vrefh rout4+ rout4- dif0 dsdr3 dsdl3 dsdr2 dsdl2 dsdr1 ak4358vq top view i2c lout2- rout2+ lout4- 37 dsdr4 24 11 dvss 12 25 dsdl1
asahi kasei [ak4358] ms0203-e-00 2003/02 - 3 - ? compatibility with ak4357 1. function & performance functions ak4357 ak4358 # of channels 6 8 dr 106db 112db 48khz/96khz tdm not available available i2c not available available dsdm control pin/register register input channel of dzf pin fixed programmable 2. pin configuration pin # ak4357 ak4358 3 dzfl1 dzf3 4 dzfr1 dzf2 5 dzf23 dzf1 7 cad1 acksn 12 nc dvss 13 dvss sdti4 18 smute i2c 19 cclk cclk/scl 20 cdti cdti/sda 21 csn csn/cad1 22 dsdm dclk 23 dclk dsdl4 24 nc dsdr4 32 dif1 rout4- 33 dif2 rout4+ 37 avss lout4- 38 avss lout4- 3. register addr bit ak4357 ak4358 00h d5 dzfm 0 01h d6 0 pw4 04h d7 att7 atte 05h d7 att7 atte 06h d7 att7 atte 07h d7 att7 atte 08h d7 att7 atte 09h d7 att7 atte 0ah d7, d6 0, 0 tdm1, tdm0 0bh not available lout4 att control 0ch not available rout4 att control 0dh not available dzf1 control 0eh not available dzf2 control 0fh not available dzf3 control
asahi kasei [ak4358] ms0203-e-00 2003/02 - 4 - pin/function no. pin name i/o function 1 lout1- o dac1 lch negative analog output pin 2 lout1+ o dac1 lch positive analog output pin 3 dzf3 o zero input detect 3 pin 4 dzf2 o zero input detect 2 pin 5 dzf1 o zero input detect 1 pin 6 cad0 i chip address 0 pin 7 acksn i auto setting mode disable pin (pull-down pin) ?l?: auto setting mode, ?h?: manual setting mode 8 pdn i power-down mode pin when at ?l?, the ak4358 is in the power-down mode and is held in reset. the ak4358 should always be reset upon power-up. 9 bick i audio serial data clock pin 10 mclk i master clock input pin an external ttl clock should be input on this pin. 11 dvdd - digital power supply pin, +4.75 +5.25v 12 dvss - digital ground pin 13 sdti4 i dac4 audio serial data input pin 14 sdti1 i dac1 audio serial data input pin 15 sdti2 i dac2 audio serial data input pin 16 sdti3 i dac3 audio serial data input pin 17 lrck i l/r clock pin 18 i2c i control mode select pin ?l?: 3-wire serial, ?h?: i 2 c bus 19 cclk/scl i control data clock pin i2c = ?l?: cclk (3-wire serial), i2c = ?h?: scl (i 2 c bus) 20 cdti/sda i/o control data input pin i2c = ?l?: cdti (3-wire serial), i2c = ?h?: sda (i 2 c bus) 21 csn/cad1 i chip select pin i2c = ?l?: csn (3-wire serial), i2c = ?h?: cad1 (i 2 c bus) 22 dclk i dsd clock pin 23 dsdl4 i dac4 dsd lch data input pin 24 dsdr4 i dac4 dsd rch data input pin 25 dsdl1 i dac1 dsd lch data input pin 26 dsdr1 i dac1 dsd rch data input pin 27 dsdl2 i dac2dsd lch data input pin 28 dsdr2 i dac2 dsd rch data input pin 29 dsdl3 i dac3 dsd lch data input pin 30 dsdr3 i dac3 dsd rch data input pin 31 dif0 i audio data interface format 0 pin 32 rout4- o dac4 rch negative analog output pin 33 rout4+ o dac4 rch positive analog output pin 34 vrefh i positive voltage reference input pin 35 avdd - analog power supply pin, +4.75 +5.25v 36 avss - analog ground pin 37 lout4- o dac4 lch negative analog output pin 38 lout4+ o dac4 lch positive analog output pin 39 rout3- o dac3 rch negative analog output pin 40 rout3+ o dac3 rch positive analog output pin 41 lout3- o dac3 lch negative analog output pin 42 lout3+ o dac3 lch positive analog output pin 43 rout2- o dac2 rch negative analog output pin 44 rout2+ o dac2 rch positive analog output pin 45 lout2- o dac2 lch negative analog output pin
asahi kasei [ak4358] ms0203-e-00 2003/02 - 5 - 46 lout2+ o dac2 lch positive analog output pin 47 rout1- o dac1 rch negative analog output pin 48 rout1+ o dac1 rch positive analog output pin note: all input pins except pull-down pin should not be left floating. absolute maximum ratings (avss, dvss=0v; note 1) parameter symbol min max units power supplies analog digital |avss-dvss| (note 2) avdd dvdd ? gnd -0.3 -0.3 - 6.0 6.0 0.3 v v v input current (any pins except for supplies) iin - 10 ma analog input voltage vina -0.3 avdd+0.3 v digital input voltage vind -0.3 dvdd+0.3 v ambient operating temperature ta -40 85 c storage temperature tstg -65 150 c note 1. all voltages with respect to ground. note 2. avss and dvss must be connected to the same analog ground plane. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (avss, dvss=0v; note 1) parameter symbol min typ max units power supplies (note 3) analog digital avdd dvdd 4.75 4.75 5.0 5.0 5.25 5.25 v v voltage reference vref avdd-0.5 - avdd v note 3. the power up sequence between avdd and dvdd is not critical. *akm assumes no responsibility for the usage beyond the conditions in this datasheet.
asahi kasei [ak4358] ms0203-e-00 2003/02 - 6 - analog characteristics (ta=25 c; avdd, dvdd=5v; vrefh=avdd; fs=44.1khz; bick=64fs; signal frequency=1khz; 24bit input data; measurement frequency=20hz 20khz; r l 2k ? ; unless otherwise specified) parameter min typ max units resolution 24 bits dynamic characteristics (note 4) fs=44.1khz bw=20khz 0dbfs -60dbfs -94 -48 -86 - db db fs=96khz bw=40khz 0dbfs -60dbfs -92 -45 -84 - db db thd+n fs=192khz bw=40khz 0dbfs -60dbfs -92 -45 - - db db dynamic range (-60dbfs with a-weighted) (note 5) 102 112 db s/n (a-weighted) (note 6) 102 112 db interchannel isolation (1khz) 90 100 db interchannel gain mismatch 0.2 0.5 db dc accuracy gain drift 100 - ppm/ c output voltage (note 7) 2.35 2.5 2.65 vpp load resistance (note 8) 2 k ? power supplies power supply current (avdd+dvdd) normal operation (pdn = ?h?, fs 96khz) (note 9) normal operation (pdn = ?h?, fs=192khz) (note 10) power-down mode (pdn = ?l?) (note 11) 56 62 10 70 85 100 ma ma a note 4. measured by audio precision system two. refer to the evaluation board manual. note 5. 100db at 16bit data. note 6. s/n does not depend on input bit length. note 7. full scale voltage (0db). output voltage scales with the voltage of vrefh pin. aout (typ. @0db) = (aout+)-(aout-) = 2.5vpp vrefh/5.0 note 8. for ac-load. 4k ? for dc-load note 9 avdd=40ma(typ), dvdd=12ma(typ)@44.1khz&5v, 16ma(typ)@96khz&5v note 10 avdd=40ma(typ), dvdd=22ma(typ)@192khz&5v note 11. all digital inputs including clock pins (mclk, bick and lrck) are held dvdd or dvss.
asahi kasei [ak4358] ms0203-e-00 2003/02 - 7 - sharp roll-off filter characteristics (ta = 25 c; avdd, dvdd = 4.75 5.25v; fs = 44.1khz; dem = off; slow = ?0?; pcm mode) parameter symbol min typ max units digital filter passband 0.05db (note 12) -6.0db pb 0 - 22.05 20.0 - khz khz stopband (note 12) sb 24.1 khz passband ripple pr 0.02 db stopband attenuation sa 54 db group delay (note 13) gd - 19.1 - 1/fs digital filter + scf frequency response 20.0khz 40.0khz 80.0khz fs=44.1khz fs=96khz fs=192khz fr fr fr - - - 0.2 0.3 +0/-0.6 - - - db db db note 12. the passband and stopband frequencies scale with fs(system sampling rate). for example, pb=0.4535fs (@ 0.05db), sb=0.546fs. note 13. the calculating delay time which occurred by digital filtering. this time is from setting the 16/24bit data of both channels to input register to the output of analog signal. slow roll-off filter characteristics (ta = 25 c; avdd, dvdd = 4.75~5.25v; fs = 44.1khz; dem = off; slow = ?1?; pcm mode) parameter symbol min typ max units digital filter passband 0.04db (note 14) -3.0db pb 0 - 18.2 8.1 - khz khz stopband (note 14) sb 39.2 khz passband ripple pr 0.005 db stopband attenuation sa 72 db group delay (note 13) gd - 19.1 - 1/fs digital filter + scf frequency response 20.0khz 40.0khz 80.0khz fs=44.khz fs=96khz fs=192khz fr fr fr - - - +0/-5 +0/-4 +0/-5 - - - db db db note 14. the passband and stopband frequencies s cale with fs. for example, pb = 0.185fs (@ 0.04db), sb = 0.888fs. dc characteristics (ta = 25 c; avdd, dvdd = 4.75 5.25v) parameter symbol min typ max units high-level input voltage low-level input voltage vih vil 2.2 - - - - 0.8 v v high-level output voltage (iout = -80a) low-level output voltage (iout = 80a) voh vol dvdd-0.4 - - - 0.4 v v input leakage current (note 15) iin - - 10 a note 15. acksn pin has internal pull-down devices, nominally 100k ? .
asahi kasei [ak4358] ms0203-e-00 2003/02 - 8 - switching characteristics (ta = 25 c; avdd, dvdd = 4.75 5.25v; c l = 20pf) parameter symbol min typ max units master clock frequency duty cycle fclk dclk 2.048 40 11.2896 36.864 60 mhz % lrck frequency normal mode (tdm0= ?l?, tdm1= ?l?) normal speed mode double speed mode quad speed mode duty cycle fsn fsd fsq duty 8 60 120 45 48 96 192 55 khz khz khz % tdm256 mode (tdm0= ?h?, tdm1= ?l?) normal speed mode high time low time fsn tlrh tlrl 32 1/256fs 1/256fs 48 khz ns ns tdm128 mode (tdm0= ?h?, tdm1= ?h?) normal speed mode double speed mode high time low time fsn fsd tlrh tlrl 32 60 1/128fs 1/128fs 48 96 khz khz ns ns pcm audio interface timing bick period bick pulse width low pulse width high bick ? ? to lrck edge (note 16) lrck edge to bick ? ? (note 16) sdti hold time sdti setup time tbck tbckl tbckh tblr tlrb tsdh tsds 81 30 30 20 20 10 10 ns ns ns ns ns ns ns dsd audio interface timing dclk period dclk pulse width low pulse width high dclk edge to dsdl/r (note 17) tdck tdckl tdckh tddd 1/64fs 160 160 -20 20 ns ns ns ns control interface timing (3-wire serial mode): cclk period cclk pulse width low pulse width high cdti setup time cdti hold time csn high time csn ? ? to cclk ? ? cclk ? ? to csn ? ? tcck tcckl tcckh tcds tcdh tcsw tcss tcsh 200 80 80 40 40 150 50 50 ns ns ns ns ns ns ns ns control interface timing (i 2 c bus mode): scl clock frequency bus free time between transmissions start condition hold time (prior to first clock pulse) clock low time clock high time setup time for repeated start condition sda hold time from scl falling (note 18) sda setup time from scl rising rise time of both sda and scl lines fall time of both sda and scl lines setup time for stop condition pulse width of spike noise suppressed by input filter fscl tbuf thd:sta tlow thigh tsu:sta thd:dat tsu:dat tr tf tsu:sto tsp - 4.7 4.0 4.7 4.0 4.7 0 0.25 - - 4.0 0 100 - - - - - - - 1.0 0.3 - 50 khz s s s s s s s s s s ns
asahi kasei [ak4358] ms0203-e-00 2003/02 - 9 - parameter symbol min typ max units reset timing pdn pulse width (note 19) tpd 150 ns note 16. bick rising edge must not occur at the same time as lrck edge. note 17. dsd data transmitting device must meet this time. note 18. data must be held for sufficient time to bridge the 300 ns transition time of scl. note 19. the ak4358 can be reset by bringing pdn= ?l?. note 20. i 2 c is a registered trademark of philips semiconductors. purchase of asahi kasei microsystems co., ltd i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system, provided the system conform to the i 2 c specifications defined by philips.
asahi kasei [ak4358] ms0203-e-00 2003/02 - 10 - ? timing diagram 1/fclk tclkl vih tclkh mclk vil dclk=tclkh x fclk, tclkl x fclk 1/fs vih lrck vil tbck tbckl vih tbckh bick vil clock timing tlrb lrck vih bick vil tsds vih sdti vil tsdh vih vil tblr audio serial interface timing (pcm mode)
asahi kasei [ak4358] ms0203-e-00 2003/02 - 11 - vih dclk vil tddd vih dsdl dsdr vil tdckh tdckl tdck audio serial interface timing (dsd normal mode, dckb = ?0?) vih dclk vil tddd vih dsdl dsdr vil tdckh tdckl tdck tddd audio serial interface timing (dsd phase modulation mode, dckb = ?0?) tcss csn vih cclk vil vih cdti vil vih vil c1 c0 r/w a4 tcckl tcckh tcds tcdh write command input timing
asahi kasei [ak4358] ms0203-e-00 2003/02 - 12 - csn vih cclk vil vih cdti vil vih vil d3 d2 d1 d0 tcsw tcsh write data input timing thigh scl sda vih tlow tbuf thd:sta tr tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto vil vih vil tsp i 2 c bus mode timing tpd vil pdn power-down timing
asahi kasei [ak4358] ms0203-e-00 2003/02 - 13 - operation overview ? d/a conversion mode the ak4358 can perform d/a conversion for both pcm data and dsd data. when dsd mode, dsd data can be input from dclk, dsdl1-4 and dsdr1-4 pins. when pcm mode, pcm data can be input from bick, sdti1-4 and lrck pins. pcm/dsd mode changes by d/p bit. when pcm/dsd mode changes by d/p bit, the ak4358 should be reset by rstn bit, pw bit (pw1=pw2=pw3=pw4= ?0?) or pdn pin. it takes about 2/fs to 3/fs to change the mode. d/p bit dac output 0 pcm 1 dsd table 1. dsd/pcm mode control ? system clock 1) pcm mode the external clocks, which are required to operate the ak4358, are mclk, lrck and bick. the master clock (mclk) should be synchronized with lrck but the phase is not critical. the mclk is used to operate the digital interpolation filter and the delta-sigma modulator. there are two methods to set mclk frequency. in manual setting mode (acks = ?0?: register 00h), the sampling speed is set by dfs0/1(table 2). the frequency of mclk at each sampling speed is set automatically. (table 3~table 5). in auto setting mode (acks = ?1?: default), as mclk frequency is detected automatically (table 6), and the internal master clock becomes the appropriate frequency (table 7), it is not necessary to set dfs0/1. when acksn = ?h?, regardless of acks bit setting the ak4358 operates by manual setting mode. when acksn = ?l?, acks bit setting is valid. all external clocks (mclk, bick and lrck) should always be present whenever the ak4358 is in the normal operation mode (pdn= ?h?). if these clocks are not provided, the ak4358 may draw excess current and may fall into unpredictable operation. this is because the device utilizes dynamic refreshed logic internally. the ak4358 should be rese t by pdn = ?l? after threse clocks are provided. if the external cl ocks are not present, the ak4358 should be in the power-down mode (pdn= ?l?). after exiting reset(pdn = ? ?) at power-up etc., the ak4358 is in the power-down mode until mclk is input. dsd interface signals (dclk, dsdl1-4, dsdr1-4) are fixed to ?h? or ?l?. dfs1 dfs0 sampling rate (fs) 0 0 normal speed mode 8khz~48khz default 0 1 double speed mode 60khz~96khz 1 0 quad speed mode 120khz~192khz table 2. sampling speed (manual setting mode) lrck mclk bick fs 256fs 384fs 512fs 768fs 64fs 32.0khz 8.1920mhz 12.2880mhz 16.3840mhz 24.5760mhz 2.0480mhz 44.1khz 11.2896mhz 16.9344mhz 22.5792mhz 33.8688mhz 2.8224mhz 48.0khz 12.2880mhz 18.4320mhz 24.5760mhz 36.8640mhz 3.0720mhz table 3. system clock example (normal speed mode @manual setting mode)
asahi kasei [ak4358] ms0203-e-00 2003/02 - 14 - lrck mclk bick fs 128fs 192fs 256fs 384fs 64fs 88.2khz 11.2896mhz 16.9344mhz 22.5792mhz 33.8688mhz 5.6448mhz 96.0khz 12.2880mhz 18.4320mhz 24.5760mhz 36.8640mhz 6.1440mhz table 4. system clock example (double speed mode @manual setting mode) lrck mclk bick fs 128fs 192fs 64fs 176.4khz 22.5792mhz 33.8688mhz 11.2896mhz 192.0khz 24.5760mhz 36.8640mhz 12.2880mhz table 5. system clock example (quad speed mode @manual setting mode) mclk sampling speed 512fs 768fs normal 256fs 384fs double 128fs 192fs quad table 6. sampling speed (auto setting mode) lrck mclk (mhz) fs 128fs 192fs 256fs 384fs 512fs 768fs sampling speed 32.0khz - - - - 16.3840 24.5760 44.1khz - - - - 22.5792 33.8688 48.0khz - - - - 24.5760 36.8640 normal 88.2khz - - 22.5792 33.8688 - - 96.0khz - - 24.5760 36.8640 - - double 176.4khz 22.5792 33.8688 - - - - 192.0khz 24.5760 36.8640 - - - - quad table 7. system clock example (auto setting mode) acksn pin acks bit clock mode 0 0 manual setting mode 0 1 auto setting mode (default) 1 0 manual setting mode 1 1 manual setting mode table 8. relationship between acksn pin and acks bit 2) dsd mode the external clocks, which are required to operate the ak4358, are mclk and dclk. the master clock (mclk) should be synchronized with dsd clock (dclk) but the phase is not critical. the frequency of mclk is set by dcks bit. all external clocks (mclk, dclk) should always be present whenever the ak4358 is in the normal operation mode (pdn= ?h?). if these clocks are not provided, the ak4358 may draw excess current because the device utilizes dynamic refreshed logic internally. the ak4358 should be reset by pdn= ?l? after threse clocks are provided. if the external clocks are not present, the ak4358 should be in the pow er-down mode (pdn= ?l?). after exiting reset(pdn = ?
asahi kasei [ak4358] ms0203-e-00 2003/02 - 15 - dcks 0 1 mclk 512fs 768fs dclk 64fs 64fs table 9. system clock (fs=44.1khz) ? audio serial interface format 1) pcm mode when pcm mode, data is shifted in via the sdti1-4 pins using bick and lrck inputs. the dif0-2 as shown in table 10 can select five serial data modes. initial value of dif0-2 bits is ?010? and dif0 bit is ored with dif0 pin. in all modes the serial data is msb-first, 2?s compliment format and is latched on the rising edge of bick. mode 2 can be used for 16/20 msb justified formats by zeroing the unused lsbs. when tdm0 = ?1?, the audio interface becomes tdm mode. in tdm256 mode (tdm1 = ?0?, table 11), the serial data of all dac (eight channels) is input to the sdti1 pin. the input data to sdti2-4 pins is ignored. bick should be fixed to 256fs. ?h? time and ?l? time of lrck should be 1/256fs at least. the serial data is msb-first, 2?s compliment format. the input data to sdti1 pin is latched on the rising edge of bick. in tdm128 mode (tdm1 = ?1?, table 12), the serial data of dac (four channels; l1, r1, l2, r2) is input to the sdti1 pin. other four data (l3, r3, l4, r4) is input to the sdti2. the input data to sdti3-4 pins is ignored. bick should be fixed to 128fs. mode tdm1 tdm0 dif2 dif1 dif0 sdti format lrck bick figure 0 0 0 0 0 0 16bit lsb justified h/l 32fs figure 1 1 0 0 0 0 1 20bit lsb justified h/l 40fs figure 2 2 0 0 0 1 0 24bit msb justified h/l 48fs figure 3 default 3 0 0 0 1 1 24bit i 2 s compatible l/h 48fs figure 4 4 0 0 1 0 0 24bit lsb justified h/l 48fs figure 2 table 10. audio data formats (normal mode) sdti bick lrck sdti 15 14 6 5 4 bick 0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1 3 2 1 0 15 14 ( 32fs ) ( 64fs ) 014 1 15 16 17 31 0 1 14 15 16 17 31 0 1 15 14 0 15 14 0 mode 0 don?t care don?t care 15:msb, 0:lsb mode 0 15 14 6 5 4 3 2 1 0 lch data rch data figure 1. mode 0 timing
asahi kasei [ak4358] ms0203-e-00 2003/02 - 16 - sdti lrck bick ( 64fs ) 09 1 10 11 12 31 0 1 9 10 11 12 31 0 1 19 0 19 0 mode 1 don?t care don?t care 19:msb, 0:lsb sdti mode 4 23:msb, 0:lsb 20 19 0 20 19 0 don?t care don?t care 22 21 22 21 lch data rch data 8 23 23 8 figure 2. mode 1,4 timing lrck bick ( 64fs ) sdti 022 1 2 24 31 0 1 31 0 1 23:msb, 0:lsb 22 1 0 don?t care 23 lch data rch data 23 30 22 224 23 30 22 1 0don?t care 23 22 23 figure 3. mode 2 timing lrck bick ( 64fs ) sdti 03 1 2 24 31 0 1 31 0 1 23:msb, 0:lsb 22 1 0 don?t care 23 lch data rch data 23 25 3 224 23 25 22 1 0 don?t care 23 23 figure 4. mode 3 timing
asahi kasei [ak4358] ms0203-e-00 2003/02 - 17 - mode tdm1 tdm0 dif2 dif1 dif0 sdti format lrck bick figure 0 1 0 0 0 n/a 0 1 0 0 1 n/a 5 0 1 0 1 0 24bit msb justified 256fs figure 5 6 0 1 0 1 1 24bit i 2 s compatible 256fs figure 6 7 0 1 1 0 0 24bit lsb justified 256fs figure 7 table 11. audio data formats (tdm256 mode) lrck bick(256fs) sdti1(i) 256 bick 22 0 l1 32 bick 22 0 r1 32 bick 22 0 l2 32 bick 22 0 r2 32 bick 22 0 l3 32 bick 22 0 r3 32 bick 22 0 l4 32 bick 22 0 r4 32 bick 22 23 23 23 23 23 23 23 23 23 figure 5. mode 5 timing lrck bick(256fs) sdti1(i) 256 bick 23 0 l1 32 bick 23 0 r1 32 bick 23 0 l2 32 bick 23 0 r2 32 bick 23 0 l3 32 bick 23 0 r3 32 bick 23 0 l4 32 bick 23 0 r4 32 bick 23 figure 6. mode 6 timing lrck bick(256fs) sdti1(i) 256 bick 22 0 l1 32 bick 22 0 r1 32 bick 22 0 l2 32 bick 22 0 r2 32 bick 22 0 l3 32 bick 22 0 r3 32 bick 22 0 l4 32 bick 22 0 r4 32 bick 23 23 23 23 23 23 23 23 23 figure 7. mode 7 timing
asahi kasei [ak4358] ms0203-e-00 2003/02 - 18 - mode tdm1 tdm0 dif2 dif1 dif0 sdti format lrck bick figure 1 1 0 0 0 n/a 1 1 0 0 1 n/a 8 1 1 0 1 0 24bit msb justified 128fs figure 8 9 1 1 0 1 1 24bit i 2 s compatible 128fs figure 9 10 1 1 1 0 0 24bit lsb justified 128fs figure 10 table 12. audio data formats (tdm128 mode) lrck bick(128fs) 128 bick l1 32 bick r1 32 bick l2 32 bick r2 32 bick l3 32 bick r3 32 bick l4 32 bick r4 32 bick sdti1(i) 22 0 22 0 22 0 22 0 23 23 23 23 22 23 sdti2(i) 22 0 22 0 22 0 22 0 23 23 23 23 22 23 figure 8. mode 8 timing lrck bick(128fs) 128 bick l1 32 bick r1 32 bick l2 32 bick r2 32 bick l3 32 bick r3 32 bick l4 32 bick r4 32 bick sdti1(i) 22 0 22 0 22 0 22 0 23 23 23 23 23 sdti2(i) 22 0 22 0 22 0 22 0 23 23 23 23 23 figure 9. mode 9 timing lrck bick(128fs) 128 bick l1 32 bick r1 32 bick l2 32 bick r2 32 bick l3 32 bick r3 32 bick l4 32 bick r4 32 bick sdti1(i) 22 0 22 0 22 0 22 0 23 23 23 23 19 sdti2(i) 22 0 22 0 22 0 22 0 23 23 23 23 19 figure 10. mode 10 timing
asahi kasei [ak4358] ms0203-e-00 2003/02 - 19 - 2) dsd mode in case of dsd mode, dif0-2 is ignored. the frequency of dc lk is fixed to 64fs. dckb bit can invert the polarity of dclk. dclk (64fs) dckb=1 dclk (64fs) dckb=0 dsdl,dsdr normal dsdl,dsdr phase modulation d1 d0 d1 d2 d0 d2 d3 d1 d2 d3 figure 11. dsd mode timing ? d/a conversion mode switching timing rstn bit d/a data d/a mode 4/fs 0 pcm data dsd data pcm mode dsd mode figure 12. d/a mode switching timing (pcm to dsd) rstn bit d/a data d/a mode 4/fs dsd data pcm data dsd mode pcm mode figure 13. d/a mode switching mode timing (dsd to pcm) caution: in dsd mode, the signal level is ranging from 25% to 75%. peak levels of dsd signal above this duty are not recommended by sacd format book (scarlet book).
asahi kasei [ak4358] ms0203-e-00 2003/02 - 20 - ? de-emphasis filter a digital de-emphasis filter is available for 32, 44.1 or 48khz sampling rates (tc = 50/15s) and is enabled or disabled with dem0 and dem1. in case of double speed and quad speed mode, the digital de-emphasis filter is always off. when dsd mode, dem0-1 is invalid. dem1 dem0 mode 0 0 44.1khz 0 1 off default 1 0 48khz 1 1 32khz table 13. de-emphasis filter control (normal speed mode) ? output volume the ak4358 includes channel independent digital output volumes (att) with 128 levels at 0.5db steps including smute. these volumes are in front of the dac and can attenuate the input data from 0db to ?63db and mute. transition time is set by ast1-0 bits(table 15) when changing levels, transitions are executed via soft changes; thus no switching noise occurs during these transitions. when atte bit is set to ?0?, the dac input data goes to ?0? immediately. it takes a time of group delay to mute the analog output. atte bit should be ?1? to enable the volume setting. atte att6-0 attenuation level 7fh 0db 7eh -0.5db 7dh -1.0db : : 02h -62.5db 01h -63.0db 1 00h smute (- ) 0 don?t care off ( ?0? ) default table 14. attenuation level of output volume mode ats1 ats0 att speed 0 0 0 1792/fs 1 0 1 896/fs 2 1 0 256/fs 3 1 1 n/a default table 15. transition time of output volume in case of mode 0, it takes 1792/fs to transit from 7fh(0db) to 00h(smute). in case mode1, it takes 896/fs to transit from 7fh(0db) to 00h(smute). in case mode2 and 3,it take s 256/fs to transit from 7fh(0db) to 00h (smute). if pdn pin goes to ?l?, att6-0 registers are initialized to 7fh.att6-0 registers go to 7fh when rstn bit is set to ?0?. when rstn bit returns to ?1?, att6-0 registers go to the set value. digital output volume function is independent of soft mute function. the setting value of the register is held when switching between pcm mode and dsd mode.
asahi kasei [ak4358] ms0203-e-00 2003/02 - 21 - ? zero detection when the input data at all channels are continuously zeros for 8192 lrck cycles, the ak4358 has zero detection like table 16. dzf pin immediately goes to ?l? if input data of ea ch channel is not zero after going dzf ?h?. if rstn bit is ?0?, dzf pin goes to ?h?. dzf pin goes to ?l? at 4~5lrck if input data of each channel is not zero after rstn bit returns to ?1?. zero detect function can be disabled by dzfe bit. in this case, all dzf pins are always ?l?. when one of pw1-4 bit is set to ?0?, the input data of dac that the pw bit is set to ?0? should be zero in order to enable zero detection of the other channels. when all pw1-4 bits are set to ?0?, dzf pin fixes ?l?. dzfb bit can invert the polarity of dzf pin. dzf pin operations dzf1 anded output of zero detection flag of each channel set to ?1? in 0dh register dzf2 anded output of zero detection flag of each channel set to ?1? in 0eh register dzf3 anded output of zero detection flag of each channel set to ?1? in 0fh register table 16. dzf pins operation ? soft mute operation soft mute operation is performed at digital domain. when the smute bit goes to ?1?, the output signal is attenuated by - during att_data att transition time (table 15) from the current att level. when the smute bit is returned to ?0?, the mute is cancelled and the output attenuation gradually changes to the att level during att_data att transition time. if the soft mute is cancelled before attenuating to - after starting the operation, the attenuation is discontinued and returned to att level by the same cycle. the soft mute is effective for changing the signal source without stopping the signal transmission. smute bit a ttenuation dzf pin att level - a out 8192/fs gd gd (1) (2) (3) (4) (1) notes: (1) att_data att transition time (table 15). for example, in normal speed mode, this time is 1792lrck cycles (1792/fs) at att_data=128. (2) the analog output corresponding to the digital input has a group delay, gd. (3) if the soft mute is cancelled before attenuating to - after starting the operation, the attenuation is discontinued and returned to att level by the same cycle. (4) when the input data at each channel is continuously zeros for 8192 lrck cycles, dzf pin of each channel goes to ?h?. dzf pin immediately goes to ?l? if input data are not zero after going dzf ?h?. figure 14. soft mute and zero detection
asahi kasei [ak4358] ms0203-e-00 2003/02 - 22 - ? system reset the ak4358 should be reset once by bringing pdn= ?l? upon power-up. the analog section exits power-down mode by mclk input and then the digital section exits power-down mode after the internal counter counts mclk during 4/fs. ? power-down the ak4358 is placed in the power-down mode by bringing pdn pin ?l? and the anlog outputs are floating (hi-z). figure 6 shows an example of the system timing at the power-down and power-up. each dac can be powered down by each power-down bit (pw1-3) ?0?. in this case, the internal register values are not initialized and the analog output is hi-z. because some click noise occurs, the analog output should be muted externally if the click noise influences system application. normal operation internal state pdn power-down normal operation gd gd ?0? data d/a out (analog) d/a in (digital) clock in mclk, lrck, bick (1) (3) (6) dzf external mute (5) (3) (1) mute on (2) (4) don?t care notes: (1) the analog output corresponding to digital input has the group delay (gd). (2) analog outputs are floating (hi -z) at the power-down mode. (3) click noise occurs at the edge of pdn signal. this noise is output even if ?0? data is input. (4) the external clocks (mclk, bick and lrck) can be stopped in the power-down mode (pdn = ?l?). (5) please mute the analog output externally if the click noise (3) influence system application. the timing example is shown in this figure. (6) dzf pins are ?l? in the power-down mode (pdn = ?l?). figure 15. power-down/up sequence example
asahi kasei [ak4358] ms0203-e-00 2003/02 - 23 - ? reset function when rstn=0, dac is powered down but the internal register values are not initialized. the analog outputs go to vcom voltage and dzfl/dzfr pins go to ?h?. figure 16 shows the example of reset by rstn bit. internal state rstn bit digital block power-down normal operation gd gd ?0? data d/a out (analog) d/a in (digital) clock in mclk,lrck,bick (1) (3) dzf (3) (1) (2) normal operation 2/fs(5) internal rstn bit 2~3/fs (6) 3~4/fs (6) don?t care (4) notes: (1) the analog output corresponding to digital input has the group delay (gd). (2) analog outputs go to vcom voltage. (3) click noise occurs at the edges(? ?) of the internal timing of rstn bit. this noise is output even if ?0? data is input. (4) the external clocks (mclk, bick and lrck) can be stopped in the reset mode (rstn = ?l?). (5) dzf pins go to ?h? when the rstn bit becomes ?0?, and go to ?l? at 2/fs after rstn bit becomes ?1?. (6) there is a delay, 3~4/fs from rstn bit ?0? to the in ternal rstn bit ?0?, and 2~3/fs from rstn bit ?1? to the internal rstn ?1?. figure 16. reset sequence example
asahi kasei [ak4358] ms0203-e-00 2003/02 - 24 - ? register control interface the ak4358 controls its functions via registers. 2 types of control mode write internal registers. in the i 2 c-bus mode, the chip address is determined by the state of the cad0 and cad1 inputs. in 3-wire mode, the cad1 input is fixed to ?1? and chip address c0 is determined by the state of the cad0 pin. pdn = ?l? initializes the registers to their default values. writing ?0? to the rstn bit resets the internal timing circuit, but the register data is not initialized. * the ak4358 does not support the read command. * when the ak4358 is in the power down mode (pdn = ?l?) or the mclk is not provided, writing to control register is invalid. function pin set-up register set-up manual setting mode o o de-emphasis x o dzfe x o smute x o audio data format dif0 o dsd mode x o attenuator x o slow roll-off response x o table 17. function table (o: supported, x: not supported) (1) 3-wire serial control mode (i2c = ?l?) 3-wire p interface pins, csn, cclk and cdti, write internal registers. the data on this interface consists of chip address (2bits, c1/0; c1 is fixed to ?1? and c0=cad0), read/write (1bit; fixed to ?1?, write only), register address (msb first, 5bits) and control data (msb first, 8bits). the ak4358 latches the data on the rising edge of cclk, so data should clocked in on the falling edge. the writing of data becomes valid by the rising edge of csn. the clock speed of cclk is 5mhz (max). cdti cclk csn c1 0 1234567 8 9 10 11 12 13 14 15 d4 d5 d6 d7 a1 a2 a3 a4 r/w c0 a0 d0 d1 d2 d3 c1-c0: chip address (c1= ?1?, c0=cad0) r/w: read/write (fixed to ?1?, write only) a4-a0: register address d7-d0: control data figure 17. control i/f timing
asahi kasei [ak4358] ms0203-e-00 2003/02 - 25 - (2) i 2 c-bus control mode (i2c= ?h?) the ak4358 supports the standard-mode i 2 c-bus (max:100khz). then the ak4358 does not support a fast-mode i 2 c-bus system (max: 400khz). figure 18 shows the data transfer sequence at the i 2 c-bus mode. all commands are preceded by a start condition. a high to low transition on the sda line while scl is high indicates a start condition (figure 22). after the start condition, a slave address is sent. this address is 7 bits long followed by an eighth bit which is a data direction bit (r/w) (figure 19). the most significant five bits of the slave address are fixed as ?00100?. the next two bits are cad1 and cad0 (device address bits). these two bits identify the specific device on the bus. the hard-wired input pins (cad1 pin and cad0 pin) set them. if the slave address match that of the ak4358 and r/w bit is ?0?, the ak4358 generates the acknowledge and the write operation is executed. if r/w bit is ?1?, the ak4358 generates the not acknowledge since the ak4358 can be only a slave-receiver. the master must generate the acknowledge-related clock pulse and release the sda line (high) during the acknowledge clock pulse (figure 23). the second byte consists of the address for control register s of the ak4358. the format is msb first, and those most significant 3-bits are fixed to zeros (figure 20). those data after the second byte contain control data. the format is msb first, 8bits (figure 21). the ak4358 generates an acknowledge after each byte has been received. a data transfer is always terminated by a stop condition generated by the master. a low to high transition on the sda line while scl is high defines a stop condition (figure 22). the ak4358 is capable of more than one byte write operation by one sequence. after receipt of the third byte, the ak4358 generates an acknowledge, and awaits the next data again. the master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. after the receipt of each data, the internal 5bits addres s counter is incremented by one, and the next data is taken into next address automatically. if the addresses exceed 1fh prior to generating the stop condition, the address counter will ?roll over? to 00h and the previous data will be overwritten. the data on the sda line must be stable during the high period of the clock. the high or low state of the data line can only change when the clock signal on the scl line is low (figure 24) except for the start and the stop condition. sda s t a r t a c k a c k s slave a ddress a c k sub a ddress(n) data(n) p s t o p data(n+x) a c k data(n+1) a c k r/w a c k figure 18. data transfer sequence at the i 2 c-bus mode 0 0 1 0 0 cad1 cad0 r/w (those cad1/0 should match with cad1/0 pins) figure 19. the first byte 0 0 0 a4 a3 a2 a1 a0 figure 20. the second byte d7 d6 d5 d4 d3 d2 d1 d0 figure 21. byte structure after the second byte
asahi kasei [ak4358] ms0203-e-00 2003/02 - 26 - scl sda stop condition start condition s p figure 22. start and stop conditions scl from master acknowledge data output by master data output by slave(ak4529) 1 9 8 start condition not acknowledge clock pulse for acknowledgement s 2 figure 23. acknowledge on the i 2 c-bus scl sda data line stable; data valid change of data allowed figure 24. bit transfer on the i 2 c-bus
asahi kasei [ak4358] ms0203-e-00 2003/02 - 27 - ? register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 1 acks slow 0 dzfe dif2 dif1 dif0 rstn 01h control 2 0 0 0 0 0 0 smute rstn 02h speed & power down control 0 pw4 dfs1 dfs0 pw3 pw2 pw1 rstn 03h de-emphasis control 0 0 0 0 0 0 dem1 dem0 04h lout1 att control atte a tt6 att5 att4 att3 att2 att1 att0 05h rout1 att control atte a tt6 att5 att4 att3 att2 att1 att0 06h lout2 att control atte a tt6 att5 att4 att3 att2 att1 att0 07h rout2 att control atte a tt6 att5 att4 att3 att2 att1 att0 08h lout3 att control atte a tt6 att5 att4 att3 att2 att1 att0 09h rout3 att control atte a tt6 att5 att4 att3 att2 att1 att0 0ah control 3 tdm1 tdm0 dcks d/p dckb dzfb ats1 ats0 0bh lout4 att control atte a tt6 att5 att4 att3 att2 att1 att0 0ch rout4 att control atte a tt6 att5 att4 att3 att2 att1 att0 0dh dzf1 control l1 r1 l2 r2 l3 r3 l4 r4 0eh dzf2 control l1 r1 l2 r2 l3 r3 l4 r4 0fh dzf3 control l1 r1 l2 r2 l3 r3 l4 r4 note: for addresses from 10h to 1fh, data must not be written. when pdn goes to ?l?, the registers are initialized to their default values. when rstn bit goes to ?0?, the only internal timing is reset, and the registers are not initialized to their default values. all data can be written to the registers even if pw1-4 or rstn bit is ?0?. acks bit is anded with the acksn pin. dif0 bit is ored with the dif pin.
asahi kasei [ak4358] ms0203-e-00 2003/02 - 28 - ? register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 1 acks slow 0 dzfe dif2 dif1 dif0 rstn default 1 0 0 1 0 1 0 1 rstn: internal timing reset 0: reset. all dzf pins go to ?h? and any registers are not initialized. 1: normal operation when mclk frequency or dfs changes, the ak4358 should be reset by pdn pin or rstn bit. dif2-0: audio data interface modes (see table 10, table 11, table 12, pcm only) initial: ?010? register bit of dif0 is ored with the dif0 pin. dzfe: data zero detect enable 0: disable 1: enable zero detect function can be disabled by dzfe bit ?0?. in this case, the dzf pins are ?l? at dzfb bit ?0? and are ?h? at dzfb bit ?1?. slow: slow roll-off filter enable (pcm only) 0: sharp roll-off filter 1: slow roll-off filter acks: master clock frequency auto setting mode enable 0: disable, manual setting mode 1: enable, auto setting mode master clock frequency is detected automatically at acks bit ?1?. in this case, the setting of dfs1-0 is ignored. when this bit is ?0?, dfs1-0 set the sampling speed mode. register bit of acks is anded with the inverted of the acksn pin. addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h control 2 0 0 0 0 0 0 smut e rstn default 0 0 0 0 0 0 0 1 rstn: internal timing reset 0: reset. all dzf pins of go to ?h? and any registers are not initialized. 1: normal operation when mclk frequency or dfs changes, the ak4358 should be reset by pdn pin or rstn bit. smute: soft mute enable 0: normal operation 1: all dac outputs soft-muted
asahi kasei [ak4358] ms0203-e-00 2003/02 - 29 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h speed & power down control 0 pw4 dfs1 dfs0 pw3 pw2 pw1 rstn default 0 1 0 0 1 1 1 1 rstn: internal timing reset 0: reset. all dzf pins go to ?h? and any registers are not initialized. 1: normal operation when mclk frequency or dfs changes, the ak4358 should be reset by pdn pin or rstn bit. pw4-1: power-down control (0: power-down, 1: power-up) pw1: power down control of dac1 pw2: power down control of dac2 pw3: power down control of dac3 pw4: power down control of dac4 all sections are powered-down by pw1=pw2=pw3=pw4=0. dfs1-0: sampling speed control (see table 2, pcm only) 00: normal speed 01: double speed 10: quad speed when changing between normal/double speed mode and quad speed mode, some click noise occurs. addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h de-emphasis control 0 0 0 0 0 0 dem1 dem0 default 0 0 0 0 0 0 0 1 dem1-0: de-emphasis response control for dac1/2/3/4 data on sdti1/2/3/4 (see table 13, pcm only) initial: ?01?, off addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h lout1 att control atte att6 att5 att4 att3 att2 att1 att0 05h rout1 att control atte att6 att5 att4 att3 att2 att1 att0 06h lout2 att control atte att6 att5 att4 att3 att2 att1 att0 07h rout2 att control atte att6 att5 att4 att3 att2 att1 att0 08h lout3 att control atte att6 att5 att4 att3 att2 att1 att0 09h rout3 att control atte att6 att5 att4 att3 att2 att1 att0 0bh lout4 att control atte att6 att5 att4 att3 att2 att1 att0 0ch rout4 att control atte att6 att5 att4 att3 att2 att1 att0 default 1 1 1 1 1 1 1 1 att6-0: attenuation level 128 levels, 0.5db step (see table 14) atte: attenuati on output enable 0: disable 1: enable
asahi kasei [ak4358] ms0203-e-00 2003/02 - 30 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ah control 3 tdm1 tdm0 dcks d/p dckb dzfb ats1 ats0 default 0 0 0 0 0 0 0 0 ats1-0: datt speed setting (see table 15) initial: ?00?, mode 0 dzfb: inverting enable of dzf 0: dzf goes ?h? at zero detection 1: dzf goes ?l? at zero detection dckb: polarity of dclk (dsd only) 0: dsd data is output from dclk falling edge 1: dsd data is output from dclk rising edge d/p: dsd/pcm mode select 0: pcm mode. sclk, sdti1-4, lrck 1: dsd mode. dclk, dsdl1-4, dsdr1-4 when d/p changes form ?1? to ?0?, the ak4358 should be reset by pdn pin, pw bit or rstn bit. when d/p changes form ?0? to ?1?, the ak4358 should be reset by pw bit or rstn bit. dcks: master clock frequency select at dsd mode (dsd only) 0: 512fs 1: 768fs tdm0-1: tdm mode select (pcm only) mode tdm1 tdm0 bick sdti sampling speed normal 0 0 32fs 1-4 normal, double, quad speed tdm256 0 1 256fs fixed 1 normal speed tdm128 1 1 128fs fixed 1-2 normal, double speed addr register name d7 d6 d5 d4 d3 d2 d1 d0 0dh dzf1 control l1 r1 l2 r2 l3 r3 l4 r4 default 1 1 1 1 1 1 1 1 l1-4, r1-4: zero detect flag enable bit for dzf1 pin 0: disable 1: enable addr register name d7 d6 d5 d4 d3 d2 d1 d0 0eh dzf2 control l1 r1 l2 r2 l3 r3 l4 r4 0fh dzf3 control l1 r1 l2 r2 l3 r3 l4 r4 default 0 0 0 0 0 0 0 0 l1-4, r1-4: zero detect flag enable bit for dzf2,3 pins 0: disable 1: enable
asahi kasei [ak4358] ms0203-e-00 2003/02 - 31 - system design figure 25 shows the system connection diagram. an evaluation board (AKD4358) is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. ak4358 top view clock gen dsp up + mode lpf lpf lpf lpf lpf lpf mute l1ch out mute r1ch out mute l2ch out mute r2ch out mute l3ch out mute r3ch out + a nalog 5v digital 5v system ground a nalog ground reset 10u 0.1u 0.1u 10u dvdd 11 mcl k 10 bic k 9 pdn 8 cad1 7 cad 0 6 dzf1 5 dzf2 4 dzf 3 3 lout1+ 2 lout1 - 1 dvss 12 avs s dsdl1 25 dsdr1 26 dsdl2 27 dsdr2 28 dsdl3 29 dsdr3 30 dif0 31 rout4- 32 rout4+ 33 vrefh 34 avdd 35 36 sdti4 13 sdti1 14 sdti2 15 sdti3 16 lrck 17 i2c 18 cclk/scl 19 cdti/sda 20 csn/cad1 21 dclk 22 dsdl4 23 dsdr4 24 48 47 46 45 44 43 42 41 40 39 38 rout1+ rout1- lout2+ lout2- rout2+ rout2- lout3+ lout3- rout3+ rout3- lout4+ 37 lout4- control dsd data cont- roller lpf mute l4ch out lpf mute r4ch out figure 25. typical connection diagram notes: - lrck = fs, bick = 64fs. - when aout drives some capacitive load, some resistor should be added in series between aout and capacitive load. - all input pins except pull-down pins should not be left floating.
asahi kasei [ak4358] ms0203-e-00 2003/02 - 32 - analog ground digital ground system controller sdti4 dvdd 13 sdti1 11 14 sdti2 15 sdti3 16 lrck 17 i2c 18 cclk/scl 19 cdti/sda 20 csn/cad1 21 dclk 22 dsdl4 23 dsdl1 25 48 rout1+ ak4358 26 27 28 29 30 31 32 33 34 35 dsdr1 dsdl2 dsdr2 dsdl3 dsdr3 dif0 rout4- rout4+ vrefh avdd 47 rout1- 46 lout2+ 45 lout2- 44 rout2+ 43 rout2- 42 lout3+ 41 lout3- 40 rout3+ 39 rout3- 38 lout4+ mcl k 10 bic k 9 pdn 8 cad1 7 cad0 6 dzf1 5 dzf2 4 dzf 3 3 lout1+ 2 lout1 - 1 dvss 12 dsdr4 24 36 avss 37 lout4- figure 26. ground layout avss and dvss must be connected to the same analog ground plane. 1. grounding and power supply decoupling avdd and dvdd are usually supplied from analog supply in system and should be separated from system digital supply. alternatively if avdd and dvdd are supplied separately, the power up sequence is not critical. avss and dvss of the ak4358 must be connected to analog ground plane . system analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. decoupling capacitor, especially 0.1 f ceramic capacitor for high frequency should be placed as near to avdd and dvdd as possible. 2. voltage reference vrefh sets the analog output range. vrefh pin is normally connected to avdd with a 0.1 f ceramic capacitor. all signals, especially clocks, should be kept away from the vrefh pin in order to avoid unwanted coupling into the ak4358. 3. analog outputs the analog outputs are full-differential outputs and 0.5 x vrefh vpp (typ) centered around the internal common voltage (about avdd/2). the differential outputs are summed externally, v aout =(aout+)-(aout-) between aout+ and aout-. if the summing gain is 1, the output range is 5.0vpp (typ @vrefh=5v). the bias voltage of the external summing circuit is supplied externally. the input data format is 2?s complement. the output voltage(v aout ) is a positive full scale for 7fffff (@24bit) and a negative full scale for 800000h (@24bit). the ideal v aout is 0v for 000000h (@24bit). the internal switched-capacitor filter and external low pass filter attenuate the noise generated by the delta-sigma modulator beyond the audio passband. dc offset on aout+/- is eliminated without ac coupling since the analog outputs are differential.
asahi kasei [ak4358] ms0203-e-00 2003/02 - 33 - 4. external analog filter it is recommended by sacd format book (scarlet book) that the filter response at sacd playback is an analog low pass filter with a cut-off frequency of maximum 50khz and a slop of minimum 30db/oct. the ak4358 can achieve this filter response by combination of the internal filter (table 18) and an external filter (figure 27). frequency gain 20khz -0.4db 50khz -2.8db 100khz -15.5db table 18. internal filter response at dsd mode 1.8k 4.3k 1.0k 1.8k 1.0k 4.3 k 270p +vop 270p -vo p aout- aout+ 3300 p analog out 2.0k 2.0k 2200p - + 2.5vpp 5.65vpp 2.5vpp figure 27. external 3rd order lpf circuit example frequency gain 20khz -0.05db 50khz -0.51db 100khz -16.8db dc gain = 1.07db table 19. 3rd order lpf (figure 27) response 3.9k 4.7k r1 3.9k r1 4.7 k 470 p +vop 470p -vop aout- aout+ 3900 p when r1=180 ? when r1=150 ? fc=90.1khz, q=0.735, g=-0.04db at 40khz fc=99.0khz, q=0.680, g=-0.23db at 40khz analog out 2.5vpp 2.5vpp 6.05vpp figure 28. external 2 nd order lpf circuit example for pcm
asahi kasei [ak4358] ms0203-e-00 2003/02 - 34 - package 1 12 48 13 7.0 9.0 0.2 7.0 9.0 0.2 0.22 0.08 48 p in lqfp ( unit:mm ) 0.10 37 24 25 36 0.16 0.07 1.40 0.05 0.13 0.13 1.70max 0 10 0.10 0.5 0.2 0.5 m ? package & lead frame material package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder (pb free) plate
asahi kasei [ak4358] ms0203-e-00 2003/02 - 35 - marking a k4358vq xxxxxxx 1 akm 1) asahi kasei logo 2) marking code: ak4358vq 3) date code: xxxxxxx(7 digits) 4) pin #1 indication important notice ? these products and their specifications are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. ? akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. ? any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: (a) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. ? it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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